library ieee;
use ieee.std_logic_1164.all;
use work.processor_types.all;

entity ir is
	port (
		instruction: in bit32;
		clock: in std_ulogic;
        reset : in std_ulogic;
        instr_sel : in std_ulogic;
		opcode: out bit6;
        reg_s : out bit5;
        reg_t : out bit5;
        reg_d : out bit5;
        reg_h : out bit5;
        func_alu : out bit6;
        jmp_addr : out bit26;
        immed     : out bit16
	);
end ir;

architecture arch_ir of ir is
    signal current_instr : bit32;
        alias op    : bit6 is current_instr(31 downto 26);
        alias func  : bit6 is current_instr(5 downto 0);
        alias rs    : bit5 is current_instr(25 downto 21);
        alias rt    : bit5 is current_instr(20 downto 16);
        alias rd    : bit5 is current_instr(15 downto 11);
        alias rh    : bit5 is current_instr(10 downto 6);
        
        alias address : bit26 is current_instr(25 downto 0);
        alias imm     : bit16 is current_instr(15 downto 0);
begin
	seq: process(clock, reset)
	begin
        if (reset='1') then
            current_instr <= (others => '0');
		elsif (rising_edge(clock)) then
            if (instr_sel = '1') then
                current_instr <= instruction;
            end if;
		end if;
	end process;
	
    reg_s <= rs;
    reg_t <= rt;
    reg_d <= rd;
    reg_h <= rh;
    opcode <= op;
    func_alu <= func;
    jmp_addr <= address;
    immed <= imm;
    
end arch_ir;
